As device critical dimensions shrink to lower than deep submicron (less than 0.25 micron), the efficient use of wafer process area becomes critical. The practice in the industry has been to add a laser mark consisting of an alphanumeric, barcode, or other type of identification mark on the front of process side of the wafer to characterize e.g., the wafer manufacturer, conductivity type, resistivity, flatness, wafer number, and device type. Automatic code readers can track the process wafers at various stages of the process and provide information on wafer movement in the fabrication process. The wafer laser mark is typically located at the wafer periphery in an exclusion zone that is within about 2 to about 3 mm from the wafer peripheral edge.
In a typical integrated circuit manufacturing process, photolithographically formed patterns and etched features are formed across the entire wafer, including the exclusion zone to reduce subsequent CMP preferential polishing in unpatterned areas, also referred to as a CMP loading effect.
According to prior art processes, in order to avoid covering up the laser mark at the wafer periphery, the practice has been to remove resist overlying the laser mark area to allow the material above the laser mark to be cleared out in a subsequent etching process.
A problem with prior art approaches is that by removing material over the laser mark area an undesirable step height is formed between the process surface and the laser mark area resulting in loss of resolution of neighboring formed feature patterns in lithographic processes due the phenomenon of defocus. The rejection of neighboring die areas is costly to yield. Further, the recessed area in the wafer process surface created by the cleared out laser mark area will act as a trap for collecting metal residue, for example copper, in subsequent integrated circuit manufacturing processes, increasing the possibility of wafer contamination including cross-process particle contamination.
Therefore, there is a need in the semiconductor processing art to develop an improved method for preserving process wafer laser markings while avoiding detrimental effects including loss of pattern resolution in neighboring active die areas.
It is therefore among the objects of the present invention to provide an improved method for preserving process wafer laser markings while avoiding detrimental effects including loss of pattern resolution in neighboring active die areas, while overcoming other shortcomings of the prior art.